Wafer flatness variation across a wafer is the number one yield limiter for semiconductor wafer fabs processing advanced semiconductor, MEMs, and LED type devices.

ASML 5500 Yield Improvement: Substrate and Chuck Flatness Monitor

Wafer flatness variation across a wafer is the number one yield limiter for semiconductor wafer fabs processing advanced semiconductor, MEMs, and LED type devices. Wafer flatness variations are typically caused by backside contamination, backside etch variations, topside film thickness variations, topside/backside CMP variations, wafer chuck flatness variations or damage, and wafer chuck vacuum variations. The yield loss resulting from wafer flatness deviations is due to critical dimension and overlay failures. ASML stepper and scanner metrology can be used to characterize and monitor wafer flatness. The Z axis height, X tilt and Y tilt is measured as the system levels and exposes every field on the wafer. This system can be used to real time monitor every field, and flag any defined field to field leveling difference limit. The ASML leveling system can be used to increase across the wafer and edge die yields by characterizing new backside/front side processes, new chucks, new backside cleaning procedures, and new chuck cleaning procedures.

 

 

ASML Leveling Rx Tilt with a wafer chuck vacuum ring >150 mm problem

 

 

 

ASML Leveling Rx Tilt for a wafer chuck backside contamination problem (arrow)

 

For more information please contact Simax Applications Engineering at Simaxlithography.com for assistance in developing a custom wafer flatness monitor application for your process.